{"id":42,"date":"2012-10-18T07:55:46","date_gmt":"2012-10-18T07:55:46","guid":{"rendered":"http:\/\/mtnstormdaq.com\/blog\/?p=42"},"modified":"2012-10-18T07:55:46","modified_gmt":"2012-10-18T07:55:46","slug":"fpga-based-daq-part-1-introduction-and-benefits","status":"publish","type":"post","link":"https:\/\/mtnstormdaq.com\/blog\/fpga-based-daq-part-1-introduction-and-benefits\/","title":{"rendered":"FPGA based DAQ part 1: Introduction and Benefits"},"content":{"rendered":"<h2 style=\"text-align: center\"><strong>A quick introduction to FPGA based technology for building DAQ systems<\/strong><\/h2>\n<p style=\"text-align: left\"><strong>What is an FPGA based DAQ system ?<\/strong><\/p>\n<p style=\"text-align: left\">There are many way to build up a DAQ (data acquisition system).\u00a0 The goal of a DAQ system is generally to take an electrical signal of some kind and convert it into digital data for further procession.\u00a0 The simplest DAQ systems are a microcontroller with a built-in ADC (analog to digital converter) and some sort of digital interface or storage device.\u00a0 An example would be a simple temperature logger with a USB port or serial output port.<\/p>\n<p style=\"text-align: left\">An FPGA based DAQ system uses an FPGA chip for handling the digital data from an ADC.\u00a0 The FPGA can incorporate its own microcontroller or interface to an external one.\u00a0 An FPGA is a microchip in which the logical functionality can be defined by the user using a special programming language called an <a title=\"HDL at wikipedia\" href=\"http:\/\/en.wikipedia.org\/wiki\/Hardware_description_language\" target=\"_blank\">HDL<\/a> such as <a title=\"Verilog article at wikpedia\" href=\"http:\/\/en.wikipedia.org\/wiki\/Verilog\" target=\"_blank\">Verilog<\/a> or <a title=\"VHDL article at wikipedia\" href=\"http:\/\/en.wikipedia.org\/wiki\/VHDL\" target=\"_blank\">VHDL<\/a>.\u00a0 Newer high level languages and graphical methods are also emerging such as: <a title=\"LabVIEW FPGA\" href=\"http:\/\/www.ni.com\/labview\/fpga\/\" target=\"_blank\">LabVIEW FPGA<\/a>, <a title=\"Simulink\" href=\"https:\/\/en.wikipedia.org\/wiki\/Simulink\" target=\"_blank\">Simulink HDL coder<\/a>, and <a title=\"System C\" href=\"https:\/\/en.wikipedia.org\/wiki\/System_C\" target=\"_blank\">System C<\/a>.\u00a0 <strong><\/strong>A more detailed description of an FPGA can be found<a title=\"Wikipedia FPGA article\" href=\"http:\/\/en.wikipedia.org\/wiki\/FPGA\" target=\"_blank\"> here<\/a>.<\/p>\n<p style=\"text-align: left\"><strong>What Benefits does FPGA technology bring to a DAQ system ?<\/strong><\/p>\n<ul>\n<li><strong><\/strong> The ability to create many standard interfaces such as <a title=\"I2S\" href=\"http:\/\/en.wikipedia.org\/wiki\/I2s\" target=\"_blank\">I2S<\/a>, <a title=\"I2C\" href=\"http:\/\/en.wikipedia.org\/wiki\/I2c\" target=\"_blank\">I2C<\/a>, <a title=\"SPI bus interface\" href=\"http:\/\/en.wikipedia.org\/wiki\/Serial_Peripheral_Interface_Bus\" target=\"_blank\">SPI<\/a>, serial i\/o, etc. as pins will allow.\u00a0 Most microcontrollers have a limited number of hardware interfaces.\u00a0 Many DAQ applications require multiple interfaces, especially where the number of ADC&#8217;s used is high.<\/li>\n<li>The ability to create non-standard interfaces.\u00a0 Some ADC&#8217;s use an SPI like or special serial interface.\u00a0 It can be difficult or impossible to interface some of these directly to a microcontroller.<\/li>\n<li>The ability to create very high speed interfaces.\u00a0 Many ADC&#8217;s have<a title=\"LVDS\" href=\"http:\/\/en.wikipedia.org\/wiki\/LVDS\" target=\"_blank\"> LVDS <\/a>interfaces allowing data rates higher than 100&#8217;s of megabits\/s and differential signaling capability.<\/li>\n<li>The ability to process many streams of data in parallel.\u00a0 An FPGA can have a separate processing channel for each data converter stream where the data is processed simultaneously and independently of the other streams.\u00a0 In addition to speed improvements, this can allow for complex cross channel triggering and processing of different channels at different rates.<\/li>\n<li>The ability to precisely time data events.\u00a0 Because each section of an FPGA can operate independently the timing system can time an event as soon as it happens.\u00a0 A microcontroller often has to wait for an interrupt to be processed to time an event.<\/li>\n<li>The ability to create many counters of any size needed.\u00a0 Most microcontrollers are limited to 3 to 6 16 bit counters.<\/li>\n<li>The ability to implement multiple microcontrollers within the same chip.\u00a0 Instead of relying on one big fast micro to do all the processing work, many independent micros can be instantiated, each with it&#8217;s own task.<\/li>\n<li>Speed.\u00a0 Many modern FPGA&#8217;s will run most of their internal logic at speeds exceeding a 100 MHz.<\/li>\n<li>Complex I\/O pins that can meet many different I\/O standards.\u00a0 Most FPGA pins can support over 25 types of I\/O standards, where micros tend to be limited to one or two.<\/li>\n<li>Deterministic response time.\u00a0 Unlike software that can be preempted and have variable response times, the HDL code is implemented as a hardware design creating a deterministic response.\u00a0 In some cases, an output signals response to an input signal can be in the sub-nanosecond time range.<\/li>\n<\/ul>\n<p style=\"text-align: left\">In summary, an FPGA bring the ability to build custom logic sub-systems that can all operate in parallel.\u00a0 This gives an FPGA based system tremendous flexibility and capability in building a DAQ system.\u00a0 In the next article the price to be paid for such capability will be investigated.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>A quick introduction to FPGA based technology for building DAQ systems What is an FPGA based DAQ system ? There are many way to build up a DAQ (data acquisition system).\u00a0 The goal of a DAQ system is generally to take an electrical signal of some kind and convert it into digital data for further&hellip; <a class=\"more-link\" href=\"https:\/\/mtnstormdaq.com\/blog\/fpga-based-daq-part-1-introduction-and-benefits\/\">Continue reading <span class=\"screen-reader-text\">FPGA based DAQ part 1: Introduction and Benefits<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[9],"tags":[],"class_list":["post-42","post","type-post","status-publish","format-standard","hentry","category-fpga-based-daq-tech","entry"],"_links":{"self":[{"href":"https:\/\/mtnstormdaq.com\/blog\/wp-json\/wp\/v2\/posts\/42","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/mtnstormdaq.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/mtnstormdaq.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/mtnstormdaq.com\/blog\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/mtnstormdaq.com\/blog\/wp-json\/wp\/v2\/comments?post=42"}],"version-history":[{"count":3,"href":"https:\/\/mtnstormdaq.com\/blog\/wp-json\/wp\/v2\/posts\/42\/revisions"}],"predecessor-version":[{"id":45,"href":"https:\/\/mtnstormdaq.com\/blog\/wp-json\/wp\/v2\/posts\/42\/revisions\/45"}],"wp:attachment":[{"href":"https:\/\/mtnstormdaq.com\/blog\/wp-json\/wp\/v2\/media?parent=42"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/mtnstormdaq.com\/blog\/wp-json\/wp\/v2\/categories?post=42"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/mtnstormdaq.com\/blog\/wp-json\/wp\/v2\/tags?post=42"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}